1. Field of the Invention
The present invention relates to a liquid-crystal display (LCD) device. More particularly, the invention relates to a substrate for a LCD device, a fabrication method thereof, and a LCD device using the substrate.
2. Description of the Related Art
As known well, the LCD device comprises a TFT (Thin-Film Transistor) array substrate on which TFTs are arranged at the respective intersections of gate electrodes and data electrodes formed in such a way as to form an array, an opposite substrate on which an opposite electrode or electrodes are formed, and a liquid crystal layer formed between these two substrates.
FIG. 1 shows an example of the pixel structure of a prior-art TFT array substrate 800. Although a plurality of pixels is actually arranged on the substrate, one pixel will be explained here for the sake of simplification of description.
This substrate 800 has a color filter 809 formed by an organic layer, which is a so-called a “color-filter-on (CF-on) TFT substrate”. With the CF-on-TFT substrate, the color filter 809 is provided on the TFT substrate 800 and therefore, the gap between the TFT array and the color filter 809 is approximately eliminated. As a result, there is an advantage that a high-resolution LCD device is realizable by progressing the miniaturization of the respective pixels while suppressing the reduction of the aperture ratio through setting the line width of the black matrix (BM) at its minimum.
With the CF-on-TFT array substrate 800, as shown in FIG. 1, a gate electrode 802 is formed on the transparent plate 801. The gate electrode 802 is covered with an inorganic gate dielectric layer 803, formed on the plate 801. On the gate dielectric layer 803, a patterned amorphous silicon (a-Si) layer 804 is formed in such a way as to overlap with the gate electrode 802. A drain electrode 806 and a source electrode 807 are formed at the opposite ends of the a-Si layer 804, respectively. The gate electrode 802, the gate dielectric layer 803, the a-Si layer 804, and the drain and source electrodes 806 and 807 constitute a TFT 820.
The TFT 820 is covered with an inorganic interlayer dielectric layer (which serves as a passivation layer) 808. The layer 808 has a contact hole 805a that exposes partially the underlying source electrode 807. The hole 805a is rectangular in horizontal cross section.
On the interlayer dielectric layer 808, a patterned color filter (i.e., a color layer) 809 is formed. The layer 808 has a contact hole 805b that exposes partially the underlying source electrode 807. The hole 805b is rectangular in horizontal cross section and is larger than the contact hole 805a of the interlayer dielectric layer 808.
On the color filter 809, a patterned light-shielding layer 810 is selectively formed at a location that overlaps with the TFT 820. The layer 810 has a function of preventing the external light from irradiating to the a-Si layer 804 and the drain electrode 806 of the TFT 820.
Moreover, an organic transparent interlayer dielectric layer 811 is formed on the color filter 809 to cover the light-shielding layer 810. The layer 811 has a contact hole 805c at a location that overlaps with the contact holes 805a and 805b, thereby partially exposing the underlying source electrode 807. The hole 805c is rectangular in horizontal cross section. The hole 805c is larger than the hole 805a but smaller than the hole 805b. 
On the interlayer dielectric layer 811, in other words, on the outermost surface 821 of the TFT array substrate 800, a pixel electrode 812 is formed. The pixel electrode 812 is extended along the inner wall of the contact hole 805c of the layer 811 and contacted with the source electrode 807 by way of the contact hole 805a of the interlayer dielectric layer 808. In this way, the pixel electrode 812 and the source electrode 807 are electrically connected to each other.
FIG. 2 shows a plan view showing the layout in the contact region 903 (i.e., in the neighborhood of the contact hole 805a) of the prior-art CF-on-TFT substrate 900 of FIG. 1.
The colored resist materials for the color filter 809 are less in chemical resistance. Therefore, if the resist materials are kept exposed during the process steps, partial loss of the filter 809 will occur through a subsequent process step or steps. Therefore, the structure of FIG. 1 is adopted in order that the organic interlayer dielectric layer 811 surely covers not only the surface of the filter 809 but also the inner wall surface of the hole 805b. In other words, as shown in FIG. 2, the boundary 909 of the color filter 809 on the side of the hole 805b and the boundary 911 of the dielectric layer 811 on the side of the hole 805c are horizontally shifted to each other (i.e., the boundary 909 is located outside the boundary 911). Thus, it is ensured that the filter 809 is covered with the layer 811. This structure may be called a “multiple contact-hole structure”.
It is popular that the thickness of the organic interlayer dielectric layer 811 is 2 to 3 μm (i.e., 2000 to 3000 nm) and the thickness of the inorganic interlayer dielectric layer 808 is several hundreds nanometers (nm). The color filter 809 with approximately the same thickness as the layer 811 is located between these dielectric layers 811 and 808. Therefore, with the prior-art TFT array substrate 800, the contact hole 805c of the layer 811 will cause a large and deep step (e.g., the height difference or depth is 4 to 6 μm). As a result, a deep depression is formed for each pixel on the outermost surface 821 of the substrate 800, as shown in FIG. 1. These depressions will disturb the orientation of the liquid crystal confined in the liquid crystal layer and thus, there arises a problem that the control of transmitting light is difficult to thereby induce leak of light. This means that the display quality degrades due to contrast reduction.
To avoid the leak of light, the source electrode 807 is typically utilized. Specifically, the shape and size of the electrode 807 are determined in such a way as to completely prevent the leak of light. In this case, however, there arises another problem that the aperture ratio will lower and the luminance of the LCD panel will deteriorate.
In particular, to form the multiple contact-hole structure (i.e., the contact region 903) as shown in FIG. 1, appropriate margins need to be provided in the respective process steps of forming the contact holes 805a, 805b, and 805c. Therefore, the hole 805b located at the horizontally outermost position will be considerably large in size, in other words, the contact region 903 (i.e., the depression shown in FIG. 1) will occupy a considerable wide area As a result, the size of the source electrode 807 needs to be considerably wider and the aperture ratio will lower conspicuously.